Integrated circuit chips receive power supply voltages, usually VCC and ground, through conductors in an integrated circuit package. While the power supply voltage applied to the external pins of the integrated circuit package may be stable and within the stated tolerance, the voltages at the power supply pads of the integrated circuit chip, under certain conditions, may not be stable and may drop below the voltage at the power supply pins of the integrated circuit package due to the inductance present in the external pins, the internal leads of the integrated circuit package, and the wire bonds between the leads of the integrated circuit package and the pads of the integrated circuit chip.
For example, when the integrated circuit is providing several output signals into large capacitive loads and is driving these loads with fast rise and fall times, the current transients, di/dt, can be appreciable, exceeding an ampere of peak current. While the series inductance of the external pin, integrated circuit package leads, and wire bonds is relatively small, on the order of 5 to 15 nanohenries, the di/dt transients times the inductance can cause a voltage differential of several volts between the external pin of the integrated circuit package and the pads on the integrated circuit chip. The result is that the noise margins of the logic levels inside the integrated circuit chip is correspondingly reduced, and if the voltage transients are great enough, unwanted logic reversals may occur inside the integrated circuit chip.
In the past, these voltage transients have been held to a safe level by restricting the rise times and fall times of the output driver stages, thereby limiting the current transients. While limiting the rise and fall times reduces the voltage transients, it also directly affects the response time of the integrated circuit, which in many cases is a critical parameter in an electronic system.
The effects of the voltage transients have also to some extent been isolated from the logic circuitry by providing separate pads on the integrated circuit chip for the power supply voltages to the output driver stages and the power supply voltages to the rest of the integrated circuit chip containing the logic circuitry, and by providing separate wire bonds on each of these pads to the power supply leads in the integrated circuit package. While this isolates the voltage transients arising from the inductance of the wire bonds, the inductance of the wire bonds is only a fraction of the total inductance arising from the external pins, the leads in the integrated circuit package, and the wire bonds.
Therefore, it can be appreciated that an integrated circuit package which decreases the voltage transients of the power supply voltage to the logic circuitry of the integrated circuit to thereby permit faster rise and fall times and/or greater worst case noise margins is highly desirable.